1. Field of the Invention
The present invention relates generally to the testing of semiconductor circuits, and more particularly, to the testing of integrated circuits by using a known pattern algorithm of defined voltage level values for both valid and invalid test data to robustly test screen and screen out manufacturing defects of the IEEE 1149.6 boundary scan circuitry on semiconductor chips.
2. Description of the Related Art
After an integrated circuit is fabricated, it will undergo electrical testing to determine if the chip operates properly or is defective. Typically the chip is placed onto a test board and electrically coupled to a testing machine. A known sequence of input data signals are then applied to input pins of the chip. In reply, the chip will process the input data signals and generate data output signals. The data output signals are then analyzed. If the state of the output signals are as expected, it indicates that the chip is operating properly. On the other hand, if the data output signals differ from the expected result, it likely means the chip is defective or there is a problem of some kind. The problem could be either with the integrity of the signal received by the chip and/or the path between the input pin where the test signal is received and the test circuitry on the chip.
Boundary Scan testing is a widely used standard in the semiconductor industry for testing the input-output circuitry on semiconductor chips. IEEE standard 1149.1 provides the specification for the boundary scan testing of digital signals, whereas IEEE 1149.6 defines the standard for analog signals. With either digital or analog devices, the IEEE standard operates essentially the same. A known sequence of input signals defined by the standard is provided to the input pins of the chip. Test receiver circuitry on the chip processes the input signals and provides data output signals to boundary scan circuitry on the chip. Again, if the output data signals are the same as the expected data signals, it is assumed the chip is operational. If output data signals are different, it is assumed that there was a problem with the integrity of the input signals and/or the path from the chip input pin to the test receiving circuitry. For more details on the digital and analog boundary scan IEEE standards, see IEEE Standard Test Access Port and Boundary-Scan Architecture (IEEE Std. 1149.1-2001) and IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks (IEEE Std. 1149.6-2003), both incorporated by reference herein for all purposes.
The problem with the aforementioned boundary scan testing standard is that a separate boundary scan piece of test equipment is required to test the chips. These test machines tend to be very expensive. In some cases, the test head used to receive the chip has to be customized for each type of chip. This customization further adds to the cost of using a boundary scan test device.
Accordingly, there is a need for a simplified boundary scan test method and test apparatus capable of performing boundary test scanning of semiconductor chips in a production test environment without the need of expensive dedicated automated test equipment.